This invention relates generally to semiconductor devices, and more particularly the invention relates to an integrated transistor logic device utilizing conductance modulation to increase transconductance and switching speed.
The CMOS transistor pair is widely used in integrated circuit logic applications. However, a limitation of such devices is speed of operation. The present invention is directed to modifying a CMOS transistor structure to include Schottky injection of minority carriers to increase transconductance and operating speed.
The use of Schottky injection in double-diffused MOS transistors (DMOS) is disclosed by Ng et al. in "P-channel Schottky Injection Field Effect Transistors," IEDM 1987, pp.770-773. As described therein, the high on resistance associated with p-channel DMOS transistors generally limits their current-handling capability. By using a p-n junction to inject a large amount of minority carrier into the drift region, very low on resistance can be achieved at the expense of slower switching speed.
However, use of a Schottky barrier p-n junction injector has provided a greater flexibility in optimizing switching speed in the Schottky Injection Field Effect Transistor (SINFET). A Schottky barrier contact is used on the place of the usual p.sup.+ drain contact. At low forward bias, the p-n junction at the anode is off and the majority of the anode current flows through the Schottky barrier contact. At higher forward bias, the p-n junction would be slightly forward-biased and current will flow through the Schottky-clamped p-n junction anode. A large amount of minority carriers is then injected from the anode into the drift region, thus causing a strong conductivity modulation in the drift region.